Novel probabilistic-based numerical tools for fast analyzing electrical properties in large-scale electronic circuits

Analysis Seminar

Speaker: Juan A. AcebronISCTE-IUL and INESC-ID/IST, TU Lisbon

Date: 10/5/2017

Time: 15h

Place: Room 1.6, building VII


During the last few years we are witnessing an exponential grown in the number of electronic components in integrated circuits (ICs). Connecting elements of the IC into a functioning whole and to the outside world requires different interconnect levels. It turns out that fabricating these interconnect structures is one of the most process-intensive and cost-sensitive portions of chip manufacturing. Among the variety of issues affecting the proper functioning of the chip, parasitic effects appear as the most critical issue degrading the circuit performance. Major effects of interconnect parasitics include the appearance of parasitic currents, distortion, reflection, and in general signal delay, specially for high-speed interconnects. It is therefore essential to have numerical tools capable to fast analyzing the electrical properties of the designed circuit and discard faulty designs before the process of manufacturing. In this talk it is presented: First, a new probabilistic algorithm  capable to extract the capacitance on multidielectric circuits with arbitrary geometry directly for a pixelized representation of the integrated circuit, and second, a novel Monte Carlo method for fast monitoring voltage and current in high-speed interconnects modeled by two-wire transmission lines.